1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device provided with a MOS (metal oxide semiconductor) transistor having a source/drain extension structure.
2. Background Art
In recent years a laser annealing technology has been expected as a heat process of the next generation to substitute for the rapid thermal annealing. This technology is a non-equilibrium heat process which is a melt recrystallization process in a period of time which is as very short as several nanoseconds, offering such advantages as a high electric activity in excess of a limit of solid solution of impurity in a semiconductor that is usually limited by the temperature and a steep impurity profile and making it possible to form source/drain of low contact resistances and more shallow and more steep impurity diffusion (extension) regions.
In order to enhance the performance of a fine CMOS transistor having a further shortened gate length, it is necessary to lower the source/drain parasitic resistances. The source/drain parasitic resistances can be roughly divided into four components; i.e., overlap resistance Rov occurring at an end portion overlapping the lower layer of the gate electrode via a gate-insulating film in the extension region, extension resistance Rext occurring in the extension region, deep source/drain resistance Rdp occurring in the deep source/drain region, and contact-junction resistance Rco occurring between the deep source/drain region and the silicide film.
[Patent document 1] JP-A-2004-235603
[Patent document 2] JP-A-2004-152888
[Non-patent document 1] Somit Talwar and David Markle, “Junction scaling using lasers for thermal annealing”, in Solid State Tech., July 2003, pp. 83-86
[Non-patent document 2] A. Shima, Y. Wang, S. Talwar, and A. Hiraiwa, “Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS”, in VLSI Symp. Tech. Dig., 2004, pp. 174-175
[Non-patent document 3] T. Ito, K. Suguro, M. Tamura, T. Taniguchi, Y. Ushiku, T. Iinuma, T. Itani, M. Yoshioka, T. Owada, Y. Imakoka, H. Murayama, and T, Kusuda, “Flash lamp annealing technology for ultra-shallow junction formation”, in Junction Technology, 2002, IWJT. Extended Abstracts of the Third International Workshop on 2-3 Dec. 2002, pp. 23-26
In order to decrease the resistances Rext, Rdp and Rco by highly activating the impurity, the annealing treatment may be effected at a high temperature after the impurity has been injected. However, the annealing treatment at a high temperature, at the same time, causes the impurity to be diffused. A concentration profile of impurity in the transverse direction is, generally, dominated by a phenomenon of diffusion. Therefore, if the annealing treatment is effected being heated at a high temperature, a steep concentration profile is not obtained and, besides, the resistance Rov increases. If the annealing treatment is effected at such a low temperature as to obtain a steep concentration profile of impurity, on the other hand, the impurity cannot be highly activated, and the resistances Rext, Rdp and Rco increase. Thus, it is difficult to decrease all of the resistances Rext, Rdp, Rco and Rov and, hence, it is difficult to decrease parasitic resistance in the source/drain to a sufficient degree. Thus, there exists a difficulty in realizing a fine CMOS transistor of high performance having a gate length of not longer than 30 nm.